1. Field of the Invention
The present invention relates to the manufacturing of integrated circuits and more particularly of BICMOS integrated circuits.
2. Discussion of the Related Art
Integrated circuit manufacturers use various technological processes to manufacture integrated circuits capable of meeting specific requirements. These technological processes are especially characterized by the number of diffusion (or implantation) steps and of masking steps. In a given technology, the manufacturer of integrated circuits desires to be capable of providing the highest possible number of basic components.
In the following description, the BICMOS process as described in European patent application 401,135 filed by the applicant in the name of the same inventor and claiming a priority of Jun. 2, 1989, will be more particularly considered. This process has the advantage of providing complementary MOS transistors and high and low voltage bipolar transistors on a single integrated circuit.
As will be described in relation with FIGS. 1A and 1B, this technological process provides three types of buried layers realized in a silicon substrate before growing an epitaxial layer in which will be formed the MOS and bipolar transistors.
FIG. 1A is a simplified diagram of an intermediate step of this technological process and schematically corresponds to FIG. 4 of the above mentioned patent application.
From the upper surface of a P-type low doped semiconductor substrate 1, have been formed, generally by implantation and annealing steps, N-type highly doped regions 2, N-type low doped regions 3, and P-type highly doped regions 4-1 and 4-2. The highly doped P regions can be realized inside regions 3, as shown by region 4-1.
The state of the device during a subsequent manufacturing step is illustrated in FIG. 1B which schematically corresponds to FIG. 5 of the above mentioned patent application. During this step, an N-type low doped epitaxial layer 5 is grown above the structure of FIG. 1A.
Transistors can be conventionally formed in the epitaxial layer 5 from the upper surface of the chip. Similarly, those skilled in the art know how to form avalanche diodes into layer 5 by using diffused regions from the upper surface. In this case, it is known that impurity diffusions from the surface or polarizations of surface isolating layers generate a drift of the breakdown voltage of the junctions during the lifetime of the diode. Additionally, in known devices, to reach a relatively high threshold voltage (12-20 volts) several diodes in series are used.